Field
Embodiments of the present disclosure generally relate to methods of patterning a hardmask layer, and more particularly to methods of patterning a hardmask layer disposed on a metal material utilized to form interconnection structures in semiconductor applications.
Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors and resistors on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for faster circuits with greater circuit densities impose corresponding demands on the materials used to fabricate such integrated circuits. In particular, as the dimensions of integrated circuit components are reduced to the sub-50 nm scale, it is necessary to use low resistivity conductive materials (e.g., copper) as well as low dielectric constant insulating materials (dielectric constant less than about 4) to obtain suitable electrical performance from such components.
The demands for greater integrated circuit densities also impose demands on the process sequences used in the manufacture of integrated circuit components. As the physical dimensions of the structures used to form semiconductor devices are pushed against technology limits, the process of accurate pattern transfer for structures that have small critical dimensions and high aspect ratios has become increasingly difficult. Copper is commonly used to form interconnects a sub-micron device nodes due to its low resistivity compared to aluminum. Copper interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or thickness of the insulating material has sub-micron dimensions, capacitive coupling may potentially occur between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to prevent capacitive coupling between adjacent metal interconnects, low dielectric constant (low-k) insulating materials (e.g. dielectric constants less than about 4.0) are needed.
Copper interconnect systems are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with copper, which is then planarized using, for example, a chemical-mechanical planarization (CMP) process. However, several disadvantages associated with copper damascene structure have become severe concerns as feature sizes continue to decrease. For example, small feature size of the metal lines generally requires higher aspect ratios, which adversely increases the difficulty in filling such features to form void free metal structures. Forming a barrier layer within high aspect features is particularly difficult. Furthermore, as feature sizes continue to decrease, the barrier layer cannot scale, thus resulting in the barrier layer becoming a greater fraction of that particular feature. Additionally, as the feature dimensions become comparable to the bulk mean free path, the effective resistivity of copper features will increase because of non-negligible electron scattering at the copper-barrier interface and at grain boundaries.
Accordingly, an alternate metal patterning using subtractive metal etching process has recently gained wide attention. A dry plasma etching process is performed to pattern the metal materials to form one or more patterns in the interconnect structure. However, current dry plasma etching processes are primarily performed by physical sputtering which results in low selectivity between the metal layer and the hardmask layer utilized during the etching process. Typically, the hardmask layer is patterned to remove a portion of the hardmask layer to expose the underlying metal layer for etching to form the interconnection structure. Conventional processes for patterning the hardmask layer over a metal layer often have poor etching stop control and low selectivity, thereby damaging the metal structure disposed under the hardmask layer. Additionally, as the hardmask layer may sometimes be fabricated from a metal containing material, which may have similar material properties to the metal layer disposed underneath, accurate control of the etch stopping point and etch selectivity becomes increasingly challenging. Additionally, selectivity to patterning layer (typically carbon based with or without Si additives) used to etch into the hardmask is becoming increasingly challenging. Furthermore, traditional methods for etch a hardmask layer utilizes aggressive halogen chemistries or oxidizing chemistries, which contaminate the nearby metal layer and may lead to non-volatile by-product formation, adversely passivating the metal surface and making it difficult to pattern the metal layer in the subsequent processes.
Furthermore, by-products generated during the hardmask etching process are often re-deposited on the sidewalls, resulting in tapered profiles, feature deformation and line width increase.
Thus, there is a need for improved methods for patterning a hardmask layer, especially the hardmask layer disposed on a metal layer, in an interconnection structure with improved process control to form accurate and desirable interconnection structures for semiconductor devices.